The present invention relates to an output circuit employed in a semiconductor integrated circuit and, more particularly, to an output circuit of an open drain type, incorporated in each of semiconductor integrated circuits, for driving a transmission line through which the circuits are interconnected.
As one of such output circuits, there has been known a Gunning Transceiver Logic output circuit (hereinafter referred to as a GTL output circuit). This GTL output circuit is disclosed in U.S. Pat. No. 5,023,488 and is employed to communicate data between a plurality of integrated circuit devices. These devices are inter-connected through a transmission line which is in turn short-circuited to a potential of a range from 1.2 to 2V, by the use of a resistance elements having its characteristic impedance equal to that of the transmission line. The GTL output circuit in each devices drives the transmission line with a logical amplitude having an amplitude of about 0.8 to 1.4V.
FIG. 3 is a circuit diagram showing a detail configuration of the above GTL output circuit. In this circuit, a P-channel MOS transistor (hereinafter referred to as a PMOS transistor) 1 and an N-channel MOS transistor (hereinafter referred to as an NMOS transistor) are connected in series between a power source line VDD and an earth or ground line GND. These lines are formed on a semiconductor integrated circuit chip. The common connected node of the transistors 1 and 2 is connected to the gate of an NMOS transistor 3. The gates of the PMOS and NMOS transistors 1 and 2 are connected in common to a data input terminal VIN. The drain of the NMOS transistor 3 is connected to an output terminal pad VOUT. Since this semiconductor integrated circuit is mounted on a package, inductive elements 14, 17, and 20, resistance elements 15, 18, and 21, and capacitive elements 16, 19, and 22 (hereinafter referred generically to as passive elements) exist parasitically in this semiconductor circuit. Specifically, a series circuit of the inductive element 14 and resistance element 15 exist parasitically between the power source line VDD and a package VDD pin, and the capacitive element 16 is connected parasitically between the connection node of the inductive element 14 and resistance element 15 and a package GND pin. A series circuit of the inductive element 17 and resistance element 18 exist parasitically between the earth line GND and package GND pin, and the capacitance element 19 is connected parasitically between the connection node of the inductive element 17 and resistance element 18 and the package GND pin. Further, a series circuit of the inductive element 20 and resistance element 21 exist parasitically between a package VOUT pin and output terminal pad VOUT, and the capacitive element 22 is connected parasitically between the connection node of the inductive element 20 and resistance element 21 and the package GND pin. A potential, fluctuating due to the influence of these passive elements, which is called "ringing", is induced at the output terminal pad VOUT, and particularly it will appears remarkably at the time when the output terminal VOUT is subjected to variations from a low to a high level.
For the purpose of suppressing the ringing, the switching operation of the NMOS transistor 3 from an ON state to an OFF state is forced to be delayed by a predetermined period of time, when a potential at the output terminal VOUT changes from a low level to a high level. In order to delay the switching operation of the NMOS transistor 3 from the turned ON state to the turned OFF state for the foregoing period of time, the switching operations of NMOS transistors 4 and 5 from the turned ON state to the turned OFF state are forced to be delayed by a delay circuit 8 by a predetermined period of time which is suitably set, and hence a potential higher than the threshold voltage of the NMOS transistor 3 is generated. Note that the value of the potential is determined by a current flowing from the output terminal OUT to the earth line GND through the NMOS transistors 4, 5, and 2 and by ON resistances of the NMOS transistors 4, 5 and 2. Thus, the NMOS transistor 3 is allowed to be slightly turned ON state for the predetermined period of time determined by the delay circuit 8, so that the ringing can be restrained.
However, when some of passive elements have undesirable large values, or when the transmission line itself have a large electrical characteristic value, the remarkable ringing takes place, which fluctuates up and down across the threshold value of the output circuit. Such the ringing can not be fully restrained. As a result, there has been a problem such that a transmission speed between the semiconductor integrated circuit is made slow.